The present invention is particularly useful in connection with compound semiconductor devices which include, as a circuit element, a field effect transistor adapted for high frequency operation. The semiconductor device is called compound in the sense that it is based on a compound semiconductor material, such as GaAs, capable of high frequency operation. Typically, the device includes multiple circuit components, and the present invention focuses on the structure of the field effect transistor.
In order to provide extremely high frequency operation, and particularly the field effect transistor component when it is used in a grounded source circuit, the source electrode of the field effect transistor must be connected to the ground plane by way of a conductor whose length is as short as possible in order to reduce grounding inductance. The ground plane is usually configured as one surface (usually the rear surface) of the substrate, plated to provide a conductive plane for bonding to the package carrying the semiconductor. In order to minimize the length of the wiring lead from the field effect transistor source to the ground plane, it has been conventional to utilize a via hole formed in the semiconductor substrate, which provides a direct connection through the substrate from the source electrode (carried on the top surface) to the ground plane (carried on the bottom surface).
FIG. 7 illustrates a prior art approach to providing a source grounded field effect transistor (sometimes referred to as a FET). The FET is formed on a compound semiconductor substrate 1, such as GaAs, having an active layer 2 on the surface thereof. Typically, the active layer 2 is formed by ion implantation, although it can be formed by epitaxial growth when desired The characterization of the active layer as "on" the surface of the substrate is intended to encompass two conditions--a first where ion implantation deposits dopant impurities into the upper structure of the substrate, and a second where a doped layer is grown over the substrate surface. Both structures associate a doped active layer with the surface, and it is unimportant to the present invention whether the active layer is actually formed within the surface of the substrate or carried by the surface--both are considered to be "on the surface" for purposes of understanding the present invention.
As is conventional, the active layer is configured to have a source region 4a, a drain region 5a, and a gate region 3a separating the source and drain regions. A source electrode 4 and drain electrode 5 are in ohmic contact with source and drain regions. A gate electrode 3, in the example formed in a gate recess 3b, forms a Schottky barrier with the active layer 2 to control current flow between the source and drain regions. The structure of the FET thus far described is conventional.
In order to enhance high frequency operation, it is desired to connect the source electrode 4 to a ground plane on the rear surface 1a of the semiconductor substrate 1. To that end, a via hole 6 is formed in the substrate, and metallization 7 is deposited on the walls of the via as well as on the rear surface 1a of the substrate. Thus, when the semiconductor substrate is mounted on a package 8 (FIG. 8) with the rear surface 1a bonded by means of solder 9 to the package 8, the metallization 7 provides a ground connection, as well as a ground plane, for the grounded source field effect transistor.
Fabrication of the device of FIG. 7 presents a number of difficulties, among them being the ability to reliably form the via 6 without damaging the structure of the field effect transistor. More particularly, the via 6 is etched from the rear surface of the substrate, and etching proceeds until the via reaches the source electrode 4. In many cases, the source electrode 4 serves as an etchant stop. Because the substrate is relatively thick, on the order of 30 to 100 microns (and often as much as 200 microns), a rapid etching process must be used. To that end, wet etching, often using tartaric acid, is utilized. The wet etching process typically does not lend itself to adequately precise control to terminate etching immediately upon reaching the active layer 2, which is usually on the order of 1 micron in thickness. Thus, the source electrode 4 is usually utilized as an etchant stop. As a result, when the semiconductor chip is assembled into a package, the solder 9 which is used to bond the rear surface of the substrate to the package, not only fills the via 6 as intended, but actually contacts and heats the source electrode 4. Since the source electrode 4 is relatively thin (typically one micron or less) and is of a low melting point material, the source electrode 4 will often melt under these conditions, resulting in a structure such as shown in FIG. 8 where the source electrode 4 is partly destroyed, and solder 9, having destroyed the electrode 4 overflows to the upper surface of the substrate, destroying the field effect transistor.
Thus, the structure of FIGS. 7 and 8 presents problems in the assembly of the fabricated semiconductor substrate 1 onto the package 8. In addition, it does not adequately lend itself to miniaturization in that the source and drain regions are typically of reasonably large area, and the associated electrodes are about of the same size and shape as the source and drain regions. As a result, a reasonably large area on the surface is taken up with the various electrodes, even though the source electrode 4 has its main connection to the ground plane at the rear of the substrate. The presence of the source electrode 4 is necessary, however, when using the wet etching technique described above, in order to serve as an etchant stop.